The many versions of analog-to-digital converters function to convert an analog input signal into a digital output signal by sampling the analog input signal at a sample rate and providing a digital representation of each sample to a specific resolution. 16 bit resolution analog-to-digital converters (ADCs) with 1 Ms/s sample rates are known.
Although each specific ADC architecture has its own inherent functionality regarding how the ADC decides what digital value is assigned to a specific sample of the input analog signal, all ADCs require calibration due to non-linearities, offsets, and/or gain and other errors. At the factory, an ADC can be calibrated in the rather straightforward manner by injecting a known analog input signal into the ADC and adjusting the ADC until the desired digital signal is output. But, for example, if a given ADC output is adjusted to be more linear at the factory, non-linearities and other errors can still result when the ADC is placed into service due to a variety of factors including changes in operating conditions such as temperature.
Thus, those skilled in the art have devised self calibrating ADCs and numerous ADC calibration techniques are known in the art. The following references are included herein by this reference: I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters,” IEEE Trans. Circ. Syst. II, pp. 185-196, March 2000; B. Murmann and B. E. Boser, “A 12b 75 MS/s Pipelined ADC using Open-Loop Residue Amplification,” ISSCC Dig. Tech. Papers, pp. 328-329, February 2003; H. Liu et al., “A 15b 20 MS/s CMOS Pipelined ADC with Digital Background Calibration,” ISSCC Dig. Tech. Papers, pp. 454-455, February 2004; K. Nair and R. Haijani, “A 96 dB SFDR 50 MS/s Digitally Enhanced CMOS Pipelined A/D Converter,” ISSCC Dig. Tech. Papers, pp. 456-457, February 2004; S. Ryu et al., “A 14b-Linear Capacitor Self-Trimming Pipelined ADC,” ISSCC Dig. Tech. Papers, pp. 464-465, February 2004; and H.-S. Lee, “A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC,” IEEE J. Solid-State Circuits, pp. 509-515, April 1994.
Some calibration techniques are non-deterministic and therefore slow since if there are 2N bits, then 22N samples are required to complete calibration. Indeed, calibration can take minutes or even as long as an hour using non-deterministic calibration techniques. During this time, the ADC is not performing its desired function of accurately converting the analog input signal into a digital signal.
Moreover, some calibration techniques are carried out in analog circuitry as opposed to digital circuitry which is problematic because of the added complexity of analog circuitry and the desirability of maintaining a purely digital system especially in CMOS implementations.
Other ADC calibration techniques function in the foreground rather than in the background. If calibration occurs in the foreground, the ADC is taken off line during calibration and the ADC does not, during calibration, perform its intended function of converting the analog input signal into a digital output signal.
Indeed, one study of the prior art reveals that no presently known ADC calibration technique is deterministic, digital (in the sense of adding no analog complexity), and also occurs in the background.
Other problems facing ADC designers are limited die area, limited power availability, and noise. That is, any viable ADC architecture and calibration scheme would limit the amount of die area occupied, the power consumed, and the noise introduced.